1. Technical Field
The present invention relates to a semiconductor package and a method for manufacturing the same and a semiconductor package module having the same.
2. Description of the Related Art
The trend for electronics has developed toward miniaturization and thinness regardless of an application field. The main focus has still been that the size decreases, while reliability should be maintained as it is or improved.
For example, in the case of products that deal with electric power, a factor for the reliability degradation, which is called heat generation is added and reliability should be considered more deeply than all other application fields.
In particular, when a plurality of power semiconductors are grouped to implement one module, issues such as thermal accumulation, property degradation by heat, and life-span reduction may serve as risk factors causing the concepts and structures of products to be changed in a second.
Meanwhile, examples of forgiving the reduction of a manufacturing cost have rapidly increased for the purpose of improving the reliability of the product.
The power semiconductor module in the related art is disclosed in Korean Patent No. 2001-0111736 (Korean unexamined publication).
The power semiconductor module in the related art uses a first substrate with a circuit and a second substrate performing a heat dissipating function, which are bonded to each other.
In this case, an adhesive containing an epoxy-based resin or solder is used in order to bond the first substrate and the second substrate and the first substrate and a semiconductor chip are bonded by using the same material as the adhesive or another adhesive.
However, the above method is disadvantageous in that a plurality of substrates are bonded or the substrate and the semiconductor chip are bonded by using the adhesive of the same material or adhesives of different materials, and as a result, heterogeneous materials are formed among the components, thereby reducing thermal and mechanical reliabilities among the components.
Further, since a method using two processes, i.e., bonding the first substrate and the second substrate and bonding the semiconductor chip onto the first substrate of bonding is used, processes as many as the components should be performed. Therefore, a process time increases and thus, efficiency decreases and as the number of processes increases, the quantity of used materials also increases, thereby causing a manufacturing cost to increase.